A Ball Grid Array (BGA) or Pin Grid Array (PGA) package for a high power dissipating integrated circuit (IC) typically contains a cavity suitable for packaging the integrated circuit. One side of the package (called the “backside” herein) will be connected to a heat sink and the other side (called the “pad side” herein) of the package will have pad areas formed for the attachment of solder balls or pins. The integrated circuit resides in the cavity, and between the backside and the pad side.
Packages have a number of layers formed usually from copper and dielectric materials. Certain layers may also be formed from solder mask or other materials. The copper layers are used to provide power planes, provide ground planes, and route signal lines from the integrated circuit to appropriate through-holes. Through-holes are formed in the layers, and the through-holes connect power planes, connect ground planes, and provide connection from power planes, ground planes, and signal lines to pad areas on the pad side of the package. The pad areas on the pad side of the package are used to mechanically and electrically couple the package and therefore the integrated circuit to a circuit board, typically through solder balls or pins.
Additionally, pad areas internal to the package are used to couple an IC to the package. One type of electrical coupling of the IC to the package is created through a process called ball-wedge wire bonding. In this case, small diameter wires made of gold, or other materials, electrically couple the IC to the package. Electrical coupling is accomplished by first bonding one end of the bond wires to pads on the surface of the IC, and the other end is then bonded to pad areas (called wedge bond pads) located inside the package cavity.
The gold bond wires typically do not bond well to copper surfaces. Consequently, when copper is used to form a wedge bond pad area, the copper is typically plated with one or more metals, one of which does bond well with common bond wire materials. By way of illustration, a nickel layer can be formed on the copper and a gold layer can be formed on the nickel layer.
The nickel and gold layers are usually formed through electroplating. In order to electroplate, conventional techniques form plating traces on a conductive surface, typically made of copper, of the pad side. The plating traces are used to electrically couple the conductive surface of the pad side of the integrated circuit package to a current source used during electroplating. A patterned mask is applied to at least the conductive surface to form the pad areas and to protect areas that will not be electroplated. Additionally, there are selected wire bonding pad areas internal to the package cavity that are also to be electroplated. These internal selected wire bonding pad areas are electrically coupled through the through-holes to the conductive surface so that the internal selected wire bonding pad areas will also be plated during electroplating. After electroplating, the plating traces are, in general, removed to improve the electrical performance of ICs operating at high frequencies, greater than approximately 2 gigahertz (GHz).
Although plating traces on the pad side of an integrated circuit package provide adequate current for electroplating, there are problems with removing the plating traces on the pad side after electroplating. A need therefore exists for processing techniques and apparatus that are not subject to these problems.